Organic electro-luminescent display device

ABSTRACT

A high-definition organic EL display device which enhances utilization efficiency of a space within a pixel is provided. In an organic EL display device in which pixels each of which is constituted of an organic El element are arranged in a matrix array, the pixel includes a pixel circuit which is configured to control an electric current supplied to the organic El element, the pixel circuit includes a capacitance, and the capacitance is arranged on a boundary of the pixels arranged adjacent to each other in a longitudinal direction of the pixels. Further, one electrode which constitutes the capacitance is used in common by the pixels arranged adjacent to each other in the longitudinal direction, and another electrode which constitutes the capacitance is separated between the pixels arranged adjacent to each other in the longitudinal direction.

CLAIM OF PRIORITY

The present application claims priority from Japanese Application JP 2007-281083 filed on Oct. 30, 2007, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an organic EL (electro-luminescent) display device, and more particularly to a circuit provided to each pixel of an organic EL display device.

2. Description of the Related Art

The inventors of the present invention have developed a pixel circuit for driving an organic EL display device as described in U.S. Pat. No. 6,950,081 (patent document 1).

The inventors of the present invention also have developed a novel pixel circuit to which a technique described in patent document 1 is applied. The inventors of the present invention have further studied a layout of a pixel circuit which can decrease an area of a pixel. With respect to a conventional layout of a pixel, U.S. Pat. No. 6,998,770 (patent document 2), U.S. Pat. No. 6,522,079 (patent document 3) and U.S. Pat. No. 6,723,576 (patent document 4) are named.

In patent documents 2 to 4, there is disclosed a conventional pixel circuit which arranges two transistors and one capacitance in one pixel. This pixel circuit is one of most typical pixel circuits. A video signal is supplied to video signal lines. A selection signal is supplied to selection signal lines. The first transistor (data fetching TFT) in the pixel is controlled in response to a selection signal so as to fetch the video signal to the pixel. The capacitance holds the difference in potential corresponding to the video signal. The second transistor (drive TFT) is controlled corresponding to a magnitude of the difference in potential held by the capacitance so as to supply a desired electric current to an organic EL element from a power source line.

The planar layout of the pixel circuit is disclosed in patent document 2 or 3. There is disclosed the structure in which one power source line is arranged in a short-side boundary between two pixels, and the second transistor is provided on left and right sides of the power source line so as to supply an electric current to an organic EL element. That is, the second transistors are arranged with a planar layout in which the second transistors are arranged in symmetry in the lateral direction with respect to the power source line, and the power source line is used in common by left and right pixels. Due to such structure, the number of power source line is reduced and, at the same time, a voltage drop is reduced thus realizing a high-definition organic EL display device.

Further, patent document 4 also discloses a conventional pixel circuit which arranges two transistors and one capacitance in one pixel.

With the technique disclosed in patent document 2 and patent document 3, however, there has been a case in which the pixel cannot accommodate the pixel circuit therein so that the high definition of the pixel cannot be acquired, a case in which it is necessary to narrow a line width of the power source line thus giving rise to a gradient in brightness, or a case in which it is necessary to reduce the capacitance thus making the gray-scale expression less than optimal.

In FIG. 13 of patent document 4, there is disclosed a pixel layout in which pixel circuits of two upper and lower pixels are arranged in line symmetry, pixel circuits of two left and right pixels are also arranged in line symmetry so that neighboring four pixels to each other are arranged in point symmetry. However, none of these patent documents discloses an idea that a constitutional element (TFT or capacitance) which constitutes the pixel can be used in common by the neighboring pixels.

SUMMARY OF THE INVENTION

The inventors of the present invention have tried to design an organic EL display device of high definition which mounts a pixel circuit to which the technique of patent document 1 is applied thereon. In this case, it is difficult to acquire the sufficient degree of definition with the use of only the pixel layout method disclosed in patent document 2 and patent document 3. Accordingly, there has been a demand for a technique which can enhance a planar layout efficiency of the pixel circuit other than the technique disclosed in patent document 2 and patent document 3.

Accordingly, it is an object of the present invention to realize an organic EL display device of high definition which can enhance space utilization efficiency in a pixel.

The inventors of the present invention have studied a possibility of common use of a constitutional element which constitutes a pixel circuit by neighboring pixels as in the case of the technique disclosed in patent document 2 where the power source line is used in common by left and right pixels, and have focused on a capacitance.

Based on such finding, according to the present invention, a capacitance is arranged on a boundary between pixels in the lateral direction, or on a boundary between pixels in the longitudinal direction, or on a boundary between pixels in the lateral direction as well as on a boundary between pixels in the longitudinal direction, and one electrode of the capacitance is used in common by both pixels.

However, the potential difference held by the capacitance differs between or among the pixels and hence, when all of four neighboring capacitances have respective one electrodes thereof used in common by the pixels, there may be a case that active matrix driving becomes practically impossible. Particularly when one electrode of the capacitance is used in common by the pixels arranged in the lateral direction of the pixels (direction normal to the video signal lines), there may be a case that a time for writing a video signal cannot be sufficiently acquired and hence, it is preferable to use one electrode of the capacitance in common by the pixels arranged in the longitudinal direction of the pixels (extension direction of the video signal lines). Particularly, in adopting the pixel circuit described in patent document 1, the video signal line is connected to the capacitance and hence, the connection amounting to two pixels is performed via a contact hole for a lower electrode of the capacitance connected to the video signal line thus enabling the efficient arrangement of the pixel circuits. In this case, to connect a semiconductor layer which constitutes one electrode of the capacitance with the line, a notch or a through hole is formed in a metal gate layer which constitutes another electrode of the capacitance.

Further, by arranging the capacitance on the boundary between two neighboring pixels arranged in the extension direction of the power source line, efficiency of a planar layout of the pixel circuits is also further enhanced thus realizing the enhancement of definition of the organic EL display device. When the power source line is used in common by the left and right pixels, the power source line is arranged on the boundary between the pixels. Accordingly, to arrange other constitutional element on the boundary, it is necessary to displace a portion of the power source line from the boundary. The displacement of the portion of the power source line allows meandering of the power source line and hence, a line length is increased and a resistance is increased whereby a voltage is liable to easily drop. In case of the organic EL display device, the voltage drop of the power source line influences an image quality and hence, it is not desirable to allow the elongation of a line length of the power source line. That is, when the power source line is used in common by the left and right pixels arranged in the extension direction of the power source line, it is desirable that one electrode of the capacitance is used in common by two neighboring pixels arranged in the longitudinal direction of the pixel which is the extension direction of the power source line.

According to the present invention, a planar layout of pixel circuits with no waste becomes possible and hence, an organic EL display device of high definition can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram of a portion of a display region of an organic EL display device;

FIG. 2 is a view showing an equivalent circuit of a pixel circuit of a first pixel (PIX11);

FIG. 3 is a view showing the layered structure for realizing the pixel circuit;

FIG. 4 is a view showing a planar layout of a semiconductor layer (FG layer);

FIG. 5 is a view showing a doping pattern of the semiconductor layer (FG layer);

FIG. 6 is a view showing a planar layout (FG layer+SG layer) of the pixel circuit; and

FIG. 7 is a view showing a planar layout (FG layer+SG layer+SD layer).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention is explained.

[Equivalent Circuit]

FIG. 1 is an equivalent circuit diagram of a portion of a display region of an organic EL display device. FIG. 1 shows the equivalent circuit of eight pixels (4×2 pixels). 4 pixels arranged on a left side of the drawing are respectively referred to as a first pixel (PIX11), a second pixel (PIX12), a third pixel (PIX13) and a fourth pixel (PIX14) from an upper left side to a lower right side. The above-mentioned 4 pixels constitute a basic pixel set PIXS. In FIG. 1, two pixel sets of PIXS (first pixel set (PIXS1) on a left side, second pixel set (PIXS2) on a right side) are arranged.

In the first pixel set (PIXS1), one first video signal line (DATA11) and one second video signal line (DATA12) are arranged for every pixel column.

In the second pixel set (PIXS2), one third video signal line (DATA21) and one fourth video signal line (DATA22) are arranged for every pixel column.

Further, one first power source line (POWER1) is arranged between the first video signal line (DATA11) and the second video signal line (DATA12). The first power source line (POWER1) is used in common by the first pixel (PIX11), the second pixel (PIX12), the third pixel (PIX13) and the fourth pixel (PIX14). That is, an electric current is supplied to the respective organic EL elements OLED (OLED11, 21, 31, 41) of the first pixel (PIX11), the second pixel (PIX12), the third pixel (PIX13) and the fourth pixel (PIX14) from the first power source line (POWER1).

In one pixel column of the first pixel set (PIXS1), eight lines which extend in the lateral direction of the pixels are arranged. The eight lines are, in order from above, constituted of a first connection power source line (MESH12), a first detection control line (MST12), a first light-emission control line (ILM12), a first reset control line (RES12), a second reset control line (RES34), a second light-emission control line (ILM34), a second detection control line (MST34), and a second connection power source line (MESH34). To express in other words, the reset control lines RES, the light-emission control lines ILM, the detection control lines MST and the connection power source lines MESH are arranged in this order from a boundary between the first pixel (PIX11) and the second pixel (PIX12) and a boundary between the third pixel (PIX13) and the fourth pixel (PIX14) toward the respective opposing boundaries (in the longitudinal direction of the pixel).

FIG. 2 shows an equivalent circuit of a pixel circuit of the first pixel (PIX11).

The first power source line (POWER1) is connected to a source of a first drive TFT (TFT111).

The first video signal line (DATA11) is connected to one end of a first holding capacitance (DCAP11).

The first reset control line (RES12) is connected to a gate of a first reset TFT (TFT112).

The first light-emission control line (ILM12) is connected to a gate of a first light-emission control TFT (TFT113).

The first detection control line (MST12) is connected to a gate of a first detection control TFT (TFT114).

A gate of the first drive TFT (TFT111) is connected to another end of the first holding capacitance (DCAP11).

A source and a drain of the first reset TFT (TFT112) are connected between a gate and a drain of the first drive TFT (TFT111).

The first reset TFT (TFT112) and the first light-emission control TFT (TFT113) are connected between the drain of the first drive TFT (TFT111) and an anode of a first organic EL element (OLED11).

The first detection control TFT (TFT114) is connected between the first video signal line (DATA11) and the anode of the first organic EL element (OLED11).

A line which connects the first drive TFT (TFT111) and the first light-emission control TFT (TFT113) is made to pass below the first reset control line (RES12) and hence, a first load capacitance (ACAP111) is generated in a portion where the line and the first reset control line (RES12) overlap with each other. Further, a line which connects the first organic EL element OLED11 and the first light-emitting control TFT113 is made to pass below the first detection control line (MST12) and hence, a second load capacitance (ACAP112) is generated in a portion where the line and the first detection control line (MST12) overlap with each other.

To summarize magnitudes of the respective capacitances, a magnitude of a channel, and kinds of NMOS and PMOS transistors, they are as follows.

The first drive TFT (TFT111) is a PMOS transistor of single gate structure with a channel length of 4 μm and a channel width of 5 to 20 μm.

The first reset TFT (TFT112) is an NMOS transistor of dual gate structure in which two separated gates having a channel length of 4 μm and a channel width of 4 μm are connected with each other in series.

The first light-emission control TFT (TFT113) is an NMOS transistor of single gate structure with a channel length of 4 μm and a channel width of 5 to 20 μm.

The first detection control TFT (TFT114) is an NMOS transistor of single gate structure with a channel length of 4 μm and a channel width of 5 to 20 μm.

The first holding capacitance (DCAP11) is set to 80 to 200 fF, and the first load capacitance (ACAP111) and the second load capacitance (ACAP112) are respectively set to 10 fF or less. Most of the respective capacitances are generated in a portion where a semiconductor layer and a metal gate layer overlap with each other by way of a gate insulation film.

A driving principle of such a circuit is described in detail in other applications and hence, in this specification, the driving principle is briefly explained.

(Driving Method)

The pixel circuit in this embodiment is driven by dividing a driving period thereof into three periods, that is, A: a period for writing a gray-scale voltage, B: a period for writing a sweep voltage, and C: a period for detecting sticking. Further, without providing the period C for detecting a sticking, the pixel circuit may be driven by dividing the driving period into two periods, that is, the period A for writing the gray-scale voltage and the period B for writing the sweep voltage.

(Period A)

A gray-scale voltage is supplied to the pixel circuit from the first video signal line (DATA11). When the first reset TFT (TFT112) which is constituted of a dual-gate TFT is turned on, the first light-emission control TFT (TFT113) is turned on and the first detection control TFT (TFT114) which is constituted of an NMOS transistor is turned off, the first organic EL element (OLED11) and the first video signal line (DATA11) are connected with each other via the first holding capacitance (DCAP11). Thereafter, when the first reset TFT (TFT112) or the first light-emission control TFT (TFT113) is turned off, a potential difference is held in the first holding capacitance (DCAP11). Here, when the first reset TFT (TFT112) is turned on, the drain and the gate of the first drive TFT (TFT111) have the same potential and hence, it is possible to write a potential difference corresponding to the gray-scale voltage in a state that Vth shifting of the first drive TFT (TFT111) is resolved.

(Period B)

Next, a sweep wave VSWEEP (a triangular wave) is supplied to the first video signal line (DATA11). The sweep wave VSWEEP is not limited to the triangular wave, and may be any waveform such as a step wave, a staircase wave or a curved wave provided that the sweep wave VSWEEP has a wave form which changes amplitude thereof with time between two values. A voltage waveform which is obtained by adding a voltage waveform of the sweep wave VSWEEP to a potential difference ΔV held by the first holding capacitance (DCAP11) is inputted to the gate of the first drive TFT (TFT111). Due to the voltage waveform obtained by combining the potential difference ΔV and the sweep waveform VSWEEP, a time in which the first drive TFT (TFT111) is turned on and a quantity of an electric current which flows in the first drive TFT (TFT111) are determined, and this period becomes a light-emitting period. Accordingly, when the potential difference held by the first holding capacitance (DCAP11) during the period for writing the gray-scale voltage is small, the light-emitting period becomes short. The supply of the sweep waveform VSWEEP to the first video signal line (DATA11) is stopped at timing that an OFF signal is inputted to the first light-emission control line (ILM12).

(Period C)

Next, in a state that an OFF voltage is supplied to the first light-emission control line (ILM12), an ON voltage is supplied to the first detection control line (MST12) so that the first organic EL element (OLED11) and the first video signal line (DATA11) are connected with each other. An electric current which flows in the first organic EL element (OLED11) in such a state is supplied to a measurement circuit via the first video signal line (DATA11). The measurement circuit is constituted of a peripheral circuit arranged outside a display region. After the measurement of the electric current is finished, an OFF voltage is supplied to the first detection control line (MST12) and the driving of the pixel circuit returns to the period A.

(Layered Structure and Planar Layout of Pixel Circuit)

FIG. 3 shows the layered structure of the organic EL display device.

The organic EL display device into which the pixel circuits according to the present invention are incorporated includes the layered structure in which a base substrate (SUB), a background layer (UC), a semiconductor layer (FG), a gate insulation film (a gate oxide film (GI layer)), a metal gate layer (SG), a first interlayer insulation film (ILI1), a source/drain metal layer (SD), a second interlayer insulation film (ILI2), a third interlayer insulation film (ILI3), pixel electrodes (AD), an element separation film (BNK), an organic layer (OEL), and a common electrode (CD) are stacked in this order.

The base substrate (SUB) is formed of a non-alkali glass plate having a thickness of 0.3 to 1.0 mm.

Next, the background layer (UC) is formed of a stacked film consisting of a silicon nitride film having a thickness of 30 nm to 300 nm and a silicon oxide film having a thickness of 30 nm to 300 nm. The background layer (UC) is formed on the whole surface of the base substrate (SUB) using a plasma CVD method.

Next, the semiconductor layer (FG) is formed on portions of the background layer (UC) where the thin film transistors (hereinafter, referred to as a TFT) are formed in an island shape. The semiconductor layer (FG) is formed such that an amorphous silicon film is formed using a plasma CVD method, the amorphous silicon film is formed into a polysilicon film by applying a crystallization annealing to the amorphous silicon film and, thereafter, the polysilicon film is formed in an island shape by dry etching using photolithography.

FIG. 5 shows doping patterns of the semiconductor layers (FG) of the first to fourth pixels (PIX11 to 14).

With respect to these doping patterns, using the boundary line between the pixels (PIX11 to 14) as an axis of symmetry, the first pixel (PIX11) and the second pixel (PIX12) are arranged in line symmetry, and the first pixel (PIX11) and the third pixel (PIX13) are arranged in line symmetry. Further, the first pixel (PIX11) and the fourth pixel (PIX14) are also arranged in point symmetry with respect to the boundary between the first pixel (PIX11) and the fourth pixel (PIX14). Accordingly, hereinafter, the explanation is made mainly with respect to the doping pattern of the first pixel (PIX11).

Further, also with respect to the metal gate layers (SG layers) and the metal source/drain layers (SD layers), in the same manner as the doping patterns, using the boundary line between the pixels (PIX11 to 14) as an axis of symmetry, the first pixel (PIX11) and the second pixel (PIX12) are arranged in line symmetry, and the first pixel (PIX11) and the third pixel (PIX13) are arranged in line symmetry. Further, the first pixel (PIX11) and the fourth pixel (PIX14) are also arranged in point symmetry with respect to the boundary between the first pixel (PIX11) and the fourth pixel (PIX14) Accordingly, hereinafter, the explanation is made mainly with respect to the metal gate layer (SG layer) and the metal source/drain layers (SD layer) of the first pixel (PIX11).

A first wiring region DP1-1, a second wiring region DP1-2, a semiconductor region PP1 of the first drive TFT (TFT111) constituted of a PMOS transistor, and a lower electrode DP2 of the first holding capacitance DCAP are doped with IIIb-group ions (nitrogen, phosphorus, arsenic and the like) of high concentration at an acceleration voltage of substantially several tens keV. Other semiconductor region is doped with Vb-group ions (boron, gallium, indium and the like) of high concentration at an acceleration voltage of substantially several tens keV. Although such doping is performed before the metal gate layer (SG) is formed, a portion of doping may be performed after the formation of the metal gate layer (SG)

FIG. 4 shows a planar layout of the first pixel (PIX11) to the fourth pixel (PIX14).

Portions where the respective constitutional components (TFT and capacitance) of the equivalent circuit of the first pixel (PIX11) shown in FIG. 1 are formed are indicated as regions A1 to A5, and contact holes for connection of the metal source/drain layer (SD) are constituted of a contact hole CH11-1, a contact hole CH11-3, a contact hole CH12, a contact hole CH13-1 and a contact hole CH13-2.

Portions where the respective constitutional components (TFT and capacitance) of the equivalent circuit of the second pixel (PIX12) shown in FIG. 1 are formed are indicated as regions B1 to B5, and contact holes for connection of the metal source/drain layer (SD layer) are constituted of a contact hole CH21-1, a contact hole CH21-3, a contact hole CH22, a contact hole CH23-1 and a contact hole CH23-2.

Portions where the respective constitutional components (TFT and capacitance) of the equivalent circuit of the third pixel (PIX13) shown in FIG. 1 are formed are indicated as regions C1 to C5, and contact holes for connection of the metal source/drain layer (SD layer) are constituted of a contact hole CH31-1, a contact hole CH31-3, a contact hole CH32, a contact hole CH33-1 and a contact hole CH33-2.

Portions where the respective constitutional components (TFT and capacitance) of the equivalent circuit of the fourth pixel (PIX14) shown in FIG. 1 are formed are indicated as regions D1 to D5, and contact holes for connection of the metal source/drain layer (SD layer) are constituted of a contact hole CH41-1, a contact hole CH41-3, a contact hole CH42, a contact hole CH43-1 and a contact hole CH43-2.

The regions A1, B1, C1 and D1 are portions where the first holding capacitance (DCAP11), a second holding capacitance (DCAP21), a third holding capacitance (DCAP31) and a fourth holding capacitance (DCAP41) are respectively formed.

The regions A2, B2, C2 and D2 are portions where the first drive TFT (TFT111), a second drive TFT (TFT211), a third drive TFT (TFT311) and a fourth drive TFT (TFT411) are respectively formed.

The regions A3, B3, C3 and D3 are portions where the first reset TFT (TFT112), a second reset TFT (TFT212), a third reset TFT (TFT312) and a fourth reset TFT (TFT412) are respectively formed.

The regions A4, B4, C4 and D4 are portions where the first light-emission control TFT (TFT113), a second light-emission control TFT (TFT213), a third light-emission control TFT (TFT313) and a fourth light-emission control TFT (TFT413) are respectively formed.

The regions A5, B5, C5 and D5 are portions where the first detection control TFT (TFT114), a second detection control TFT (TFT214), a third detection control TFT (TFT314) and a fourth detection control TFT (TFT414) are respectively formed.

Next, as the gate oxide film (GI layer), a silicon oxide film having a thickness of 50 to 200 nm which is referred to as a TEOS film in general is formed over the whole surface of the base substrate (SUB) using a plasma CVD method.

The contact hole CH11-1, the contact hole CH11-2, the contact hole CH11-3, the contact hole CH12, the contact hole CH13-1 and the contact hole CH13-2 are formed simultaneously with the formation of the contact hole in the first interlayer insulation film (ILI1) described later after the formation of the first interlayer insulation film (ILI1). The metal gate layer (SG layer) is not formed above such a region and hence, the metal gate layer (SG layer) does not constitute an etching stopper whereby the collective etching can be performed. These contact holes may formed by either wet etching or dry etching. For reducing the number of photo masking, the metal gate layer (SG layer) and the semiconductor layer (FG layer) are not directly connected with each other but are connected with each other by way of the metal source/drain layer (SD layer).

Next, as the metal gate layer (SG layer), a film having a thickness of 50 to 200 nm and made of high-melting-point metal such as molybdenum, tungsten, chromium, titanium, tantalum or alloy of these metals is formed on the gate oxide film( GI layer) at an area (channel area) where the metal gate layer (SG layer) overlaps with the semiconductor layer (FG layer). The film is formed by sputtering and, thereafter, the film is patterned by wet etching.

FIG. 6 shows the planar layout (FG+SG) of the pixel circuits of the first pixel (PIX1) to the fourth pixel (PIX14) explained heretofore. FIG. 6 is a view obtained by adding a planar layout of the metal gate layers (SG layers) to a planar layout of the semiconductor layers (FG layers) shown in FIG. 5.

In the first pixel set (PIXS1), ten lines/electrodes of the metal gate layer (SG layer) which extend in the row direction (lateral direction of the pixel) are arranged. In the drawing, in order from above, a first connection power source line (MESH12), the first detection control line (MST12), the first light-emission control line (ILM12), the first reset control line (RES12), a first holding capacitance electrode (CDEN1), a second holding capacitance electrode (CDEN2), a third holding capacitance electrode (CDEN3), a fourth holding capacitance electrode (CDEN4), the second reset control line (RES34), the second light-emission control line (ILM34), the second detection control line (MST34), and a second connection power source line (MESH34) are arranged. The first holding capacitance electrode (CDEN1) and the third holding capacitance electrode (CDEN3) constitute upper electrodes of the first holding capacitance (DCAP11) and the third holding capacitance (DCAP13) and metal gates of the first drive TFT (TFT111) and the third drive TFT (TFT311) To express the arrangement of these components in other words, the holding capacitances CDEN, the reset control lines RES, the light-emission control lines ILM, the detection control lines MST, and the connection power source lines MESH are arranged in this order from the boundary between the first pixel (PIX11) and the third pixel (PIX13) toward the opposing boundaries respectively (in the longitudinal direction in the drawing).

The further detailed planar layout is explained in conjunction with the first pixel (PIX11).

The first holding capacitance electrode (CDEN1) is arranged in the region A1 and is used as an upper electrode of the first holding capacitance (DCAP11). By arranging the contact hole CH11-4 on a projecting portion of the first holding capacitance electrode (CDEN1), the first holding capacitance electrode (CDEN1) is connected with the first reset TFT (TFT112) Further, another projecting portion of the first holding capacitance electrode (CDEN1) is used as a gate electrode of the first drive TFT (TFT111) A boundary between the first holding capacitance electrode (CDEN1) and the third holding capacitance electrode (CDEN3) is arranged to constitute the boundary between the first pixel (PIX11) and the third pixel (PIX13). That is, a capacitance lower electrode amounting to two longitudinally neighboring pixels is formed on a boundary between the pixels which are arranged adjacent to each other in the longitudinal direction as a continuous member, and capacitance upper electrodes amounting to two longitudinally neighboring pixels are formed on the capacitance lower electrode by way of the gate insulation film GI in a state that the capacitance upper electrodes are separated from each other by a boundary line between longitudinally neighboring pixels.

In the first pixel (PIX11), the first reset control line (RES12) is curved upwardly in the drawing (in the longitudinal direction of the pixel) by 0 degrees, 45 degrees, 90 degrees, 135 degrees and 180 degrees in this order. Before and after curving the first reset control line (RES12), the first reset control line (RES12) is made to pass above the region A3 of the semiconductor layer (FG layer) twice by way of the gate oxide film (GI layer) thus constituting the dual gate of the first reset TFT (TFT112). This constitution is provided for ensuring a space for arranging the contact holes CH11-2, CH12 at the respective curved portions of the first reset control line (RES12). Further, the first reset control line (RES12) is made to pass above the semiconductor layer (FG layer) one more time by way of the gate oxide film (GI layer) after being curved. The semiconductor layer (FG layer) arranged below the first reset control line (RES12) constitutes a line, and a second load capacitance (ACAP112) is generated at an intersecting portion of the first reset control line (RES12) and the semiconductor layer (FG layer). Further, the first reset control line (RES12) is made to intersect with the first power source line (POWER1) by way of the interlayer insulation film ILI1 at an intermediate portion of the curved portion of the first reset control line (RES12) (an intermediate portion of the curved portion of the second reset control line (RES34)) A width of the power source line (POWER1) arranged in a region surrounded by the first reset control line (RES12) is decreased. Such constitution is provided for ensuring a region necessary for arranging the contact hole CH12 at the curved portion of the first reset control line (RES12).

In the first pixel (PIX11), the first light-emission control line (ILM12) is curved upwardly in the drawing by 0 degrees, 45 degrees, 135 degrees and 180 degrees in this order. In the first pixel (PIX11) of the drawing, the first light-emission control line (ILM12) is made to pass above the wide width portion of the semiconductor layer (FG layer) one time at the upwardly curved portion of the first light-emission control line (ILM12) by way of the gate oxide film (GI layer). The first light-emission control TFT (TFT113) is formed on an intersection portion of the first light-emission control line (ILM12) and the semiconductor layer (FG layer). The contact hole CH13-2 can be arranged in a region formed between the first light-emission control line (ILM12) and the first detection control line (MST12) due to such curving and hence, it is possible to realize an efficient layout of the pixel circuit.

In the first pixel (PIX11), the first detection control line (MST12) is curved downwardly by 0 degrees, 45 degrees, 90 degrees, 135 degrees and 180 degrees in this order. Due to such curving, the contact hole CH13-2 can be arranged in a region formed between the first detection control line (MST12) and the first light-emission control line (ILM12) and hence, it is possible to realize an efficient layout of the pixel circuit. Further, due to such curving, the contact hole CH13-1 and the contact hole CH14 also can be arranged in a region formed between the first detection controlline (MST12) and the first connection power source line (MESH12) (the second connection power source line (MESH34)) and hence, it is possible to realize a further efficient planar layout of the pixel circuit.

The first connection power source line (MESH12) and the second connection power source line (MESH34) are respectively connected to the first power source line (POWER1) and the second power source line (POWER2) of the metal source/drain layer (SD layer) using a contact hole CHm12 and a contact hole CHm34.

Next, the first interlayer insulation film (ILI1) having a film thickness of 100 nm to 500 nm and made of silicon oxide is formed on an upper layer of the metal gate layer (SG layer) and the TEOS film using a plasma CVD method.

Thereafter, as described previously, the holes other than the contact hole CH14 which is connected to the pixel electrode (AD), that is, the contact hole CH11-1, the contact hole CH11-2, a contact hole CH11-3, a contact hole CH11-4, the contact hole CH12, the contact hole CH13-1 and the contact hole CH13-2 are formed in the interlayer insulation film (ILI1). These contact holes are formed by wet etching.

Next, the metal source/drain layer (SD layer) is formed of a stacked-layer line consisting of a high-melting-point metal layer, a low-resistance metal layer and a high-melting-point metal layer. Thicknesses of the respective layers are set to 10 nm to 100 nm, 100 nm to 500 nm and 10 nm to 100 nm. The high-melting-point metal layer is made of metal such as molybdenum, tungsten, chromium, titanium, tantalum or alloy of these metals. The low-resistance metal layer is made of metal mainly constituted of aluminum or alloy thereof. The metal source/drain layer (SD layer) is formed by sputtering and, thereafter, is formed into a predetermined pattern by wet etching or dry etching.

FIG. 7 shows a planar layout (FG layer+SG layer+SD layer) of the pixel circuits of the first pixel (PIX11) to the fourth pixel (PIX14).

FIG. 7 shows the planar layout formed by adding a layout of the metal source/drain layer (SD layer) to a layout of the planar layout shown in FIG. 6.

As the metal source/drain layer (SD layer), the first power source line (POWER1), the first video signal line (DATA11), the second video signal line (DATA12), the low-resistance films formed of the contact hole CH11-3, the contact hole CH11-4 and the contact hole CH12, and lines between the contact hole CH13-1 and the contact hole CH14 are formed.

The first power source line (POWER1) is arranged linearly such that an axis of the first power source line (POWER1) overlaps with a boundary line (boundary line which extends in the longitudinal direction of the pixels) between the first pixel (PIX11) and the second pixel (PIX12) and a boundary line (boundary line which extends in the longitudinal direction of the pixels) between the third pixel (PIX13) and the fourth pixel (PIX14). The first power source line (POWER1) is connected to not only pixel circuits of pixels of one pixel column in the longitudinal direction in the drawing (the first pixel (PIX11) and the third pixel (PIX13)) but also pixel circuits of pixels of two pixel columns in the longitudinal direction in the drawing (the first pixel (PIX11), the second pixel (PIX12), the third pixel (PIX13) and the fourth pixel(PIX14)). Further, the first power source line (POWER1) has a width thereof narrowed at a portion thereof arranged adjacent to the contact holes and widened at other portions thereof. This change in width is also set in symmetry in the lateral direction and hence, the power source line sandwiched by the contact hole is narrowed.

The first video signal line (DATA11) is a line used in common by pixels of one column in the longitudinal direction (the first pixel (PIX11) and the third pixel (PIX13)). Between two neighboring power source lines consisting of the first power source line (POWER1) and the second power source line (POWER2), two video signal lines consisting of the second video signal line (DATA12) and the third video signal line (DATA21) are arranged.

Next, the second interlayer insulation film (ILI2) is formed of a silicon nitride film having a thickness of 0.2 to 1 μm. That is, the second interlayer insulation film (ILI2) is formed as a film by a plasma CVD method and is formed into the predetermined pattern by dry etching.

Then, as the third interlayer insulation film (ILI3), an organic insulation film having a film thickness of 0.3 to 5 μm is formed using a material selected from a polyimide resin, an acryl resin or an epoxy resin. After applying such a resin, predetermined patterning is performed using a step in the same manner as patterning of a resist in a photolithography step. Here, the contact hole CH14 connected to the pixel electrode (AD) is formed. The third interlayer insulation film (ILI3) may be formed of an inorganic insulation film made of silicon oxide or silicon nitride.

Next, the first reflection film (REF1) having a film thickness of 10 to 100 nm is formed using high-melting-point metal such as molybdenum, tungsten, chromium, titanium, tantalum or alloy of these metals. Further, the second reflection film (REF2) having a film thickness of 50 to 200 nm is formed using metal mainly constituted of aluminum or silver or alloy which contains these metals. The first reflection film (REF1) and the second reflection film (REF2) are respectively formed by sputtering and, thereafter, these films are collectively etched by wet etching.

Next, as the pixel electrode (AD), an ITO film having a film thickness of 10 to 200 nm is formed. Here, the ITO film is formed also above the contact hole CH14 connected to the metal source drain layer (SD layer).

A following relationship is established between the planar pattern of the first reflection film (REF1), the planar pattern of the second reflection film (REF2) and the planar pattern of the pixel electrode (AD).

An outer periphery of the second reflection film (REF2) is arranged inside an outer periphery of the first reflection film (REF1). That is, the second reflection film (REF2) is arranged above the first reflection film (REF1) without projecting from the first reflection film (REF1).

An outer periphery of the pixel electrode AD is arranged outside the outer periphery of the second reflection film (REF2) and the outer periphery of the first reflection film (REF1) That is, the pixel electrode (AD) is arranged above the second reflection film (REF2) and the first reflection film (REF1) in a state that the whole outer periphery of the pixel electrode (AD) projects from the second reflection film (REF2) and the first reflection film (REF1).

Next, the element separation film (BNK) having a film thickness of 0.3 μm to 5 μm is formed using a material selected from a polyimide resin, an acryl resin or an epoxy resin using a step in the same manner as patterning of a resist in a photolithography step. Here, the element separation film (BNK) is formed so as to cover not only gaps defined between the first reflection films (REF1), the second reflection films (REF2) and the pixel electrodes (AD) but also the outer peripheries of all of the first reflection films (REF1), the second reflection films (REF2) and the pixel electrodes (AD) from the outside while exposing a center portion of each pixel electrode (AD)

Next, after the formation of the element separation film (BNK), oxygen plasma treatment is applied to the element separation film (BNK). This treatment is provided for adjusting a work function on a surface of the pixel electrode (AD).

Next, organic layers (OEL) are formed on an exposure regions of the pixel electrodes (AD) surrounded by the element separation film (BNK) and an upper surface of the element separation film (BNK). To arrange stripe-shaped boundaries on the upper surface of the element separation film (BNK), the organic layers of a stripe pattern of three colors in which the pixels of same color are arranged in the same direction as the longitudinal direction of the pixels are formed. The organic layers (OEL) are formed by a vapor deposition method.

The organic layer (OEL) is constituted of a hole injection/transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.

The hole injection/transport layer may be formed by using, for example, a tetraarylbenzidine compound (triphenyldiamine; TPD), an aromatic third class amine, a hydrazone derivative, a carbazole derivative, a triazole derivative, an imidazole derivative, an oxadiazole derivative including amino group, a polythiophene derivative, a copper phthalocyanine derivative, or the like.

A material which can be used as a light-emitting-layer material is not specifically limited provided that the material is made of a host material which has an electron-and-hole transporting ability, and a dopant which is added to the host material, emits a fluorescent light or a phosphorous light by re-coupling of the host material and forms a light emitting layer by co-vapor-deposition. For example, as the host material, a complex such as tris(8-quinolinolato) aluminum, bis(8-quinolinolato) magnesium, bis(benzo{f}-8-quinolinolato) zinc, bis(2-methyl-8-quinolinolato) aluminum oxide, tris(8-quinolinolato) indium, tris(5-methyl-8-quinolinolato) aluminum, 8-quinolinolato lithium, tris(5-chloro-8-quinolinolato) gallium, bis(5-chloro-8-quinolinolato) calcium, (5,7-dichloro-8-quinolinolato) aluminum, tris(5,7-dibromo-8-hydroxyquinolinolato) aluminum, and poly [zinc(II)-bis(8-hydroxy-5-quinolinyl)methan], an anthracene derivative, a carbazole derivative, or the like can be used.

Further, the dopant is a material which captures electrons and holes in a host material and emits light by re-coupling. For example, the red dopant may be formed of a pyran derivative, the green dopant may be formed of a coumarin derivative, and the blue dopant may be formed of a substance which emits fluorescent light such as an anthracene derivative or a substance which emits phosphorescence such as an iridium complex and a pyridinato derivative.

A material which can be used as an electron-transport-layer material is not specifically limited provided that the material exhibits electron transport property and can be easily formed into a charge-transfer complex by co-deposition with alkali metal and, for example, a metal complex such as tris(8-quinolinolato) aluminum, tris(4-methyl-8-quinolinolato) aluminum, bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum, bis [2-[2-hydroxyphenyl]benzooxazolato]zinc, 2-(4-biphenylyl)-5-(4-tert-butyphenyl)-1,3,4-oxadiazol, 1,3-bis [5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl] benzene or the like can be used.

The electron injection layer is formed by a co-vapor-deposition method using a material which exhibits electron donating property to a material which is used for forming the electron transport layer. For example, as the material of the electron injection layer, it is possible to use any material selected from alkali metal such as lithium or cesium, alkali earth metal such as magnesium or calcium, a metal group including rare earth metal, or oxide, halide or carbide of these materials, provided that the material exhibits electron donating property.

As the common electrode (CD), a transparent conductive film having a film thickness of 10 to 200 nm and made of IZO, ZnO, ITZO or the like is formed by sputtering as the electrode used in common by all pixels. Although not shown in the drawing, above the common electrode, auxiliary lines may be formed in a state that the lines made of aluminum, zinc or the like are formed on the element separation film by a vapor deposition method or the like.

The above-mentioned planar layout of the pixel circuits has following technical features.

(1) The first pixel (PIX11) and the second pixel (PIX12) which are arranged adjacent to each other in the lateral direction are arranged in line symmetry with respect to the longitudinal boundary line, and the third pixel (PIX13) and the fourth pixel (PIX14) which are arranged adjacent to each other in the lateral direction are arranged in line symmetry with respect to the longitudinal boundary line.

(2) The first pixel (PIX11) and the third pixel (PIX13) which are arranged adjacent to each other in the longitudinal direction are arranged in line symmetry with respect to the lateral boundary line, and the second pixel (PIX12) and the fourth pixel (PIX14) which are arranged adjacent to each other in the longitudinal direction are arranged in line symmetry with respect to the lateral boundary line.

(3) The lower electrode which is formed of the semiconductor layer (FG layer) of the first holding capacitance (DCAP11) and the lower electrode which is formed of the semiconductor layer (FG layer) of the third holding capacitance (DCAP31) are formed in a continuous pattern. That is, the lower electrode of the capacitance is used in common by the first pixel (PIX11) and the third pixel (PIX13).

(4) The lower electrode which is formed of the semiconductor layer (FG layer) of the second holding capacitance (DCAP21) and the lower electrode which is formed of the semiconductor layer (FG layer) of the fourth holding capacitance (DCAP41) are formed in a continuous pattern. That is, the lower electrode of the capacitance is used in common by the second pixel (PIX12) and the fourth pixel (PIX14).

(5) The contact hole is arranged at the center (the center in the longitudinal direction of the pixel) of the continuous pattern of the lower electrode of the first holding capacitance (DCAP11) and the lower electrode of the third holding capacitance (DCAP31).

(6) The contact hole is arranged at the center (the center in the longitudinal direction of the pixel) of the continuous pattern of the lower electrode of the second holding capacitance (DCAP21) and the lower electrode of the fourth holding capacitance (DCAP41).

When lower electrode of the first holding capacitance (DCAP11) and the lower electrode of the third holding capacitance (DCAP31) are separated from each other or when the lower electrode of the second holding capacitance (DCAP21) and the lower electrode of the fourth holding capacitance (DCAP41) are separated from each other, it is necessary to form two contact holes. According to the technical features (5) and (6), the lower electrode of the first holding capacitance (DCAP11) and the lower electrode of the third holding capacitance (DCAP31) are formed in a continuous pattern, and the lower electrode of the second holding capacitance (DCAP21) and the lower electrode of the fourth holding capacitance (DCAP41) are formed in a continuous pattern and hence, the electrical connection is established even with the use of only one contact hole. The contact hole may be formed of two separate contact holes. 

1. An organic EL display device in which pixels each of which is constituted of an organic El element are arranged in a matrix array, wherein the pixel includes a pixel circuit which is configured to control an electric current supplied to the organic El element, the pixel circuit includes a capacitance, and the capacitance is arranged on a boundary of the pixels arranged adjacent to each other in a longitudinal direction of the pixels.
 2. An organic EL display device according to claim 1, wherein one electrode which constitutes the capacitance is continuously formed between the pixels arranged adjacent to each other in the longitudinal direction of the pixels, and another electrode which constitutes the capacitance is separately formed between the pixels arranged adjacent to each other in the longitudinal direction of the pixels.
 3. An organic EL display device according to claim 1, wherein one electrode which constitutes the capacitance is formed of a silicon film doped with phosphorous with higher concentration than a channel layer.
 4. An organic EL display device according to claim 1, wherein one electrode which constitutes the capacitance is connected to a video signal line via one contact hole.
 5. An organic EL display device according to claim 1, wherein one electrode which constitutes the capacitance is separated from the pixel arranged adjacent to the pixel in the lateral direction of the pixels.
 6. An organic EL display device according to claim 1, wherein the pixel circuits arranged in the pixels are arranged in line symmetry with respect to the boundary of the pixels for every pixel in the longitudinal direction of the pixel.
 7. An organic EL display device according to claim 1, wherein the pixel circuits arranged in the pixels are arranged in line symmetry with respect to the boundary of the pixels for every pixel in the lateral direction of the pixel.
 8. An organic EL display device comprising: a plurality of pixels each of which is constituted of an organic EL element; power source lines which are configured to supply an electric current to the organic EL elements; and video signal lines which are configured to supply video signals to the pixels, wherein the pixel includes: a transistor which is connected between the power source line and the organic EL element; and a capacitance which is connected between the transistor and the video signal line, and a contact hole is formed at a position adjacent to a portion of the power source line where a line width is narrowed.
 9. An organic EL display device according to claim 8, wherein the power source line is sandwiched between the contact holes arranged adjacent to each other. 